Efficient High Though put Multi Standard Transform Core Realization on FPGA

An efficient architecture of 1D CSDA MST core is designed using CSDA (Common Sharing Distributed Arithmetic) to achieve high-throughput rate supporting multistandard transformations at low cost. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardware-sharing capability. Conventional distributed arithmetic (DA) is popular in application specific integrated circuit (ASIC) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, a new DA architecture called NEDA is proposed, aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in digital signal processing (DSP) applications. Compared with other architectures available, it has a great improvement on computing speed and reducing area. And also, an CLA (carry look ahead adder) is implemented and to achieve low power and high throughput discrete cosine transform (DCT) design. While conventional approaches use the original DCT algorithm, the proposed architecture uses the recursive DCT algorithm and requires less area than the conventional approaches, regardless of the memory reduction techniques employed in the ROM Accumulators (RACs).The main strategy aims to reduce the nonzero elements using CSDA algorithm and hence few adders are required in the adder-tree circuit.